A Pareto-Optimal Multi-filter Architecture on FPGA for Image Processing Applications
October 01, 2019
Majida Kazmi, Arshad Aziz, Dur e Shahwar
Circuits Systems and Signal Processing - Volume 38, Issue 10, Pages 4762-4786
Multi-Resolution Transforms Based Hybrid Feature Extraction Technique for Differentiating Glioma Grades.
July 20, 2018
RAZIA ZIA, PERVEZ AKHTAR, ARSHAD AZIZ, DUR E SHAHWAR KUNDI
International Journal of Wavelets, Multiresolution and Information Processing -
A low-power SHA-3 designs using embedded digital signal processing slice on FPGA
October 01, 2016
Dur e Shahwar, Arshad Aziz
Computers & Electrical Engineering - Volume 55, Pages 138-152
A high performance ST-Box based unified AES encryption/decryption architecture on FPGA
March 01, 2016
Dur e Shahwar, Arshad Aziz, Nassar Ikram
Microprocessors and Microsystems - Volume 41, Pages 37-46
Resource Efficient Implementation of the Keccak, Skein & JH Algorithms on a Reconfigurable Platform
January 01, 2016
Arshad Aziz, Dur-e-Shahwar Kundi, Kashif Latif
Cankaya University Journal of Science and Engineering - Volume 13, No. 1, Pages 40-57
Implementation of T-box/T-1-Box Based AES Design on Latest Xilinx FPGA
October 01, 2015
Arshad Aziz, Dur-e-Shahwar Kundi
Mehran University Research Journal of Engineering and Technology - Volume 35 , Issue 4, Pages 441-446
Logically Grouped Reduced-set Implementation of SHA3-256 on FPGA
August 01, 2015
Arshad Aziz, Dur-e-Shahwar Kundi
Mehran University Research Journal of Engineering and Technology - Volume 34, Issue S1, Pages 13-20
Area Efficient S-Box Approach for SubByte Transformation in AES
August 01, 2015
Arshad Aziz, Dur-e-Shawar Kundi, Saleha Zaka
Mehran University Research Journal of Engineering and Technology - Volume 34, Issue S1, Pages 63-68
An efficient single unit T-box/T-1-box implementation for 128-bit AES on FPGA
June 01, 2015
Dur e Shahwar, Arshad Aziz, Majida Kazmi
Security and Communication Networks - Volume 8, Issue 9, Pages 1725-1731
FPGA Based Compact and Efficient Full Image Buffering for Neighborhood Operations
February 28, 2015
Majida Kazmi, Arshad Aziz, Pervez Akhter, Dur e Shahwar
Advances in Electrical and Computer Engineering - Volume 15, Issue 1, Pages 95-104
FPGA Implementation of Advance Encryption Standard Using Xilinx System Generator
April 01, 2014
Arshad Aziz, Alia Arshad, Kanwal Aslam, Dur-e-Shahwar Kundi
Asian Journal of Applied Sciences - Volume 02, Issue 02, Pages 190-198
Resource efficient implementation of T-Boxes in AES on Virtex-5 FPGA
April 30, 2010
Dur e Shahwar, Arshad Aziz, Nasar Ikram
Information Processing Letters - Volume 110, Issue 10, Pages 373-377
Non Sub-sampled Contourlet Transform based Feature Extraction technique for Differentiating Glioma Grades using MRI Images
August 19, 2017 - August 20, 2017
Arshad Aziz, Razia Zia, Pervez Akhtar, Maroof Ali Shah, Dur-e-Shahwar Kundi
30th Australasian Joint Conference on Artificial Intelligence - Australia
Compact Implementation of SHA3-512 on FPGA
June 12, 2014 - June 13, 2014
Arshad Aziz, Alia Arshad, Dur-e-Shahwar Kundi
IEEE Conference on Information Assurance and Cyber Security (CIACS) - Pakistan
Software implementation of Standard Hash Algorithm (SHA-3) Keccak on Intel core-i5 and Cavium Networks Octeon Plus embedded platform
June 15, 2013 - June 20, 2013
Arshad Aziz, Aisha Malik, Dur- e-Shahwar Kundi, Moiz Akhter
2nd Mediterranean Conference on Embedded Computing (MECO) - Mexico
Compact Implementation of Skein-256 Hash Function on FPGA
May 27, 2012 - May 30, 2012
Arshad Aziz, Dur-e-Shahwar Kundi
Spring Congress on Engineering and Technology - China
A Compact AES Encryption Core on Xilinx FPGA
February 17, 2008 - February 18, 2008
Arshad Aziz, Dur-e-Shahwar Kund, Saleha Zaka, Qurat-Ul-Ain
2nd IEEE International Conference on Computer, Control and Communication - Pakistan